The present invention relates to memory controllers in semiconductor integrated circuits and, more particularly to the use of error correction codes (ECCs) with multi-port memory controllers.
Error correction codes have been used to detect and correct errors in data that has been stored in memory or transmitted from one location to another. A simple ECC code is based on parity. A parity bit is added to a group of data bits, such as a data word, and has a logic state that is selected to make the total number of 1s (or 0s) in the data word either even or odd. The original data word is then transmitted or stored along with the additional parity bit as a modified data word. In a memory storage system, when the modified data word is read from memory an ECC detection circuit checks the parity of the modified data word against an expected value. If the parity is correct, the ECC detection circuit assumes there are no bit errors. If the parity is incorrect, the ECC detection circuit assumes there is an error in the stored data.
More complex ECC codes have also been used for enabling not only detection of additional errors but also correction of some of the detected errors. For example, a single-error correction, double-error detection (SEC-DED) Hamming code adds enough additional parity bits to enable the detection circuit to detect and correct any single-bit error in a data word and detect two-bit errors. Other types of error correction codes include convolutional (tree) codes and block codes. In these types of ECC codes, one or more data words are divided into blocks of data and each block of data is encoded into a longer block of data. With convolution codes, the encoding of one block of data depends on the state of the encoder as well as the data to be encoded. With block codes, each block of data is encoded independently from every other block of data.
Recently, there has been an increase in interest in using ECC codes while writing data to and reading data from integrated circuit memories, such as random access memories (RAMs), dynamic random access memories (DRAMs), and double data rate (DDR) DRAMs. The use of ECC codes with integrated circuit memories has been found to increase manufacturing yield of integrated circuit memories and reduce problems with random cell defects in memory arrays.
Integrated circuit memories are typically controlled by a memory controller, which regulates access to and from the memory. A typical memory controller is implemented as a state machine on an integrated circuit. The memory can be either embedded on the same integrated circuit as the memory controller or implemented as an external device. The ECC support circuitry is typically implemented within the memory controller state machine.
With each new memory technology such as current SDR, DDR, RLDRAM, FCRAM, etc., typically a new memory controller must be designed to interface to these new technologies with its associated electrical and functional protocol. If the architecture of a memory controller is such that it contains ECC support circuitry, then migrations to new memory technologies require that each new memory controller be designed with this same support circuitry. Write data paths must be modified to include the ECC generation circuitry and the merging of the original data bits with the ECC bits. The read data path must be modified to include the ECC detection and correction circuitry. This complicates the design of these newer memory controllers.
Another disadvantage of implementing the ECC support circuitry as part of the memory controller state machine is that the ECC support circuitry reduces overall performance of multi-port memory systems when multiple access requests need to be serviced by the memory controller. If the memory controller is busy processing ECC codes during a read or write operation for one port, the other ports must wait until the entire read or write operation has completed before gaining access to the memory controller. This difficulty becomes worse during “read/modify/write” operations. A read/modify/write operation is required when a bus master attempts to write a smaller number of bits than the width of an ECC block. An ECC block is defined the basic unit of data to which the ECC bits apply. When partial ECC block writes are executed, the memory controller must read the original data that is stored in the memory location being written to and then merge the read data with the new data to form a full ECC block. The appropriate ECC bits are then generated for the full ECC block and then written with the ECC block into the memory address.
This read/modify/write operation can take a number of extra clock cycles to complete. If the memory controller is busy performing a read/modify/write operation when another memory access request occurs from a second port, the second port must wait until the read/modify/write operation for the first port is completed. This increases the memory access latency of the second port and can degrade overall performance.
Improved memory controller systems are therefore desired which are modular in design and capable of supporting ECC codes without significantly degrading performance of the system.